Scope of ASHES
ASHES 2019 welcomes submissions on any aspect of hardware security.
This includes, but is not limited to:
- Fault injection, side channels, hardware Trojans, and countermeasures
- Tamper sensing and tamper protection
- New physical attack vectors or methods
- Secure sensors
- Device fingerprinting and hardware forensics
- Lightweight hardware solutions
- Secure, efficient, and lightweight hardware implementations
- Security of reconfigurable and adaptive hardware
- Emerging computing technologies in security
- New designs and materials in hardware security
- Nanophysics and nanotechnology in hardware security
- Physical unclonable functions and new/emerging variants thereof
- Item tagging, secure supply chains, and product piracy
- Intellectual property protection and content protection
- Scalable hardware solutions for large numbers of players/endpoints
- Hardware security and machine learning:
Secure hardware implementations of machine learning algorithms,
machine learning in side channel attacks, etc.
- Hardware security in emerging application scenarios:
Internet of Things, smart home, automotive and autonomous systems,
wearable computing, pervasive and ubiquitous computing, etc.
- Architectural factors and hardware security in the cloud
- Electronic voting machines
- Nuclear weapons inspections and control
- Physical layer and wireless network security
- Anti-forensic attacks and protection:
Hardware virtualization, anti-forensic resilient memory acquisition, etc.
- Mobile devices, smart cards, and chip cards
- Architectural factors in hardware security, isolation versus encryption
- Secure hardware for multiparty computation
- Integration of hardware root of trust and PUFs
- Quality metrics for secure hardware
- Conformance and evaluation of secure hardware
- Formal treatments, proofs, standardization,
or categorization of hardware-related techniques
(incl. surveys and systematization of knowledge papers)
To account for the special nature of hardware security as a rapidly developing discipline, the workshop offers four different categories of papers:
- Full papers, with up to 10 pages in ACM double column format (including references and appendices), and a 25 min presentation timeslot at the workshop (including questions).
- Short papers, with up to 6 pages in ACM double column format (including references and appendices), and a 15 min presentation timeslot at the workshop (including questions).
- Wild and crazy (WaC) papers, with 3 to 6 pages in ACM double column format (excluding appendices and references), and 15 min presentation timeslot at the workshop (including questions). WaC papers are meant to target groundbreaking new methods and paradigms for hardware security. Their focus lies on novelty and potential impact, and on the plausibility of their argumentation, but not on a full demonstration or complete implementation of their ideas. They are reviewed and assessed as such. Wild and crazy papers must bear the prefix “WaC:” in their title from the submission onwards.
- Systematization of knowledge (SoK) papers, with up to 12 pages in ACM double column format (excluding appendices and references), and a 25 min presentation timeslot at the workshop (including questions). SoK papers shall evaluate, systematize, and contextualize existing knowledge. They should serve the community by fostering and structuring the development of a particular subarea within hardware security. Ideally, but not necessarily, they might provide a new view on an established, important subarea, support or challenge long-standing beliefs with compelling evidence, or present a convincing new taxonomy. They will be reviewed and assessed as such. Systematization of knowledge papers must bear the prefix “SoK:” in the title from the submission onwards.
- Paper submission deadline: July 5, 2019 23:59:59 EDT.
- Acceptance notification: August 7, 2019
- Camera-ready deadline: August 30, 2019
Conflicts of Interest
(Following the ACM SIGMOD 2015 CfP)
During submission of a research paper, the submission site will request information about conflicts of
interest of the paper’s authors with program committee (PC) members. It is the full responsibility of all authors of a paper to identify all and only their potential conflict-of-interest PC members, according to the following definition. A paper author has a conflict of interest with a PC member if and only if one or more of the following conditions holds:
- The PC member is a co-author of the paper.
- The PC member has been a co-worker in the same company or university within the past two years.
- The PC member has been a collaborator within the past two years.
- The PC member is or was the author’s primary thesis advisor, no matter how long ago.
- The author is or was the PC member’s primary thesis advisor, no matter how long ago.
- The PC member is a relative or close personal friend of the author.
Papers with incorrect or incomplete conflict of interest information as of the submission closing time
are subject to immediate rejection.
Call for Papers in PDF Format
The call for papers can be downloaded as a flyer in PDF format here